Various host systems may be implemented with one or more programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices). PLDs are typically programmed with configuration data each time they are booted (e.g., when a host system is turned on or otherwise reset). This programming takes time as configuration data is loaded into the PLD and written into various memories therein to configure the PLD for operation.
In some cases, the programming time may exceed the maximum allowable boot time permitted under a particular operational standard (e.g., a protocol and/or other operational requirements). In particular, the Peripheral Computer Interface Express (PCIe) standard may require PCIe compatible devices to respond to configuration requests within 100 ms of being reset, which many conventional PLDs cannot meet.
Conventional techniques to reduce PLD programming time include, for example, using parallel flash memories to provide configuration data to the PLD more rapidly. However, such implementations are often cost prohibitive. Accordingly, there is a need for a PLD and related programming techniques that can satisfy the boot time constraints of one or more operational standards.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.